This invention is generally related to the generation of a forward body bias (FBB) voltage for field effect transistors (FETs), and particularly to robust generation circuits that maintain a constant FBB despite variations in the manufacturing process, the operating temperature, and supply voltage.
Forward body biasing reduces process induced variations in short channel field effect transistors (FETs). N-channel FETs (NFETs) have sources, drains, and bodies (also known as bulks) with voltages Vsource, Vdrain, and Vbody. N-channel metal oxide semiconductor field effect transistors (NMOSFETs) are examples of NFETs. NFETs are zero body biased when Vbody=Vsource, reverse body biased when Vbody less than Vsource, and forward body biased when Vbody greater than Vsource. The amount of FBB for NFETs is measured by Vbodyxe2x88x92Vsource, which equals Vbody when Vsource is at ground on a return line voltage (sometimes referred to as Vss). P-channel FETs (PFETs) have sources, drains, and bodies with voltages Vsource, Vdrain, and Vbody. P-channel channel metal oxide semiconductor field effect transistors (PMOSFETs) are examples of PFETs. PFETs are zero body biased when Vbody=Vsource, reverse body biased when Vbody greater than Vsource, and forward body biased when Vbody less than Vsource. The amount of FBB for PFETs is measured by Vsource Vbody, Vbody which equals Vccxe2x88x92Vbody in cases where Vsource is at the power supply line voltage Vcc (sometimes referred to as Vdd).
The threshold voltage (Vt) of a FET decreases as the FET becomes more forward biased and increases as the FET becomes less forward biased or more reverse biased. The leakage of a FET increases as the FET becomes more forward biased and decreases as the FET becomes less forward biased or more reverse biased.
Circuits that provide stable voltage references independent of manufacturing process, power supply voltage and operating temperature are needed for many applications, including accurate FBB generation. Among the techniques available for realizing a voltage reference are the use of zener diodes, the use of the difference in threshold voltage between enhancement and depletion FETs, and bandgap-based circuits. The first two methods are not suitable for complex, advanced integrated circuits (ICs) because the breakdown voltage of the zener diode is significantly higher than the supply voltages used to operate such ICs. Depletion FETs may not be available in complimentary metal oxide semiconductor (CMOS) IC fabrication processes. Because of these limitations, bandgap circuits are used extensively. Although bandgap reference circuits are extremely accurate, they are complex and demand considerable design time.
In applications such as FBB generation in CMOS ICs, a complimentary pair of FBB reference voltages often needs to be provided, where one is measured with respect to the power supply voltage (e.g. Vdd or Vcc) and the other is measured with respect to the power return voltage (Vss or ground). The voltage with respect to Vdd, called Vrefc, is applied to a PFET whereas the voltage with respect to Vss, called Vrefs, is applied to an NFET. Thus, for a PFET whose source is shorted to Vdd, a FBB of approximately 0.4 Volts is obtained by setting the bulk terminal of the device to Vrefc which is 0.4 Volts less than Vdd. In the same way, for an NFET whose source is shorted to Vss, the FBB of 0.4 Volts is applied by setting the bulk terminal to Vrefs which is 0.4 Volts greater than Vss. One limited solution for generating Vrefc and Vrefs is to build a separate generator for each. That, however, requires double the area, power, and circuit design effort, and is therefore an inefficient solution.